深圳市云迪科技有限公司

FEATURES 1.6 GHz differential clock input 3 programmable dividers Divide-by in range from1 to 32 Phase select for coarse delay adjust 2 independent 1.6 GHz LVPECL clock outputs Additive broadband output jitter 225 fs rms 1 independent 800 MHz/250 MHz LVDS/CMOS clock output Additive broadband output jitter 300 fs rms/290 fs rms Time delays up to 10 ns Device configured with 4-level logic pins Space-saving, 32-lead LFCSP APPLICATIONS Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure ATE 

The AD9514 features a multi-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. There are three independent clock outputs. Two of the outputs are LVPECL, and the third output can be set to either LVDS or CMOS levels. The LVPECL outputs operate to 1.6 GHz, and the third output operates to 800 MHz in LVDS mode and to 250 MHz in CMOS mode. Each output has a programmable divider that can be set to divide by a selected set of integers ranging from 1 to 32. The phase of one clock output relative to another clock output can be set by means of a divider phase select function that serves as a coarse timing adjustment.